1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a MOS transistor subjected to micropatterning and a method of manufacturing the same.
2. Description of the Prior Art
The structure of a conventional MOS transistor, particularly a conventional CMOS transistor, will be described in accordance with its manufacturing process. First of all, as shown in FIG. 1A, boron is ion-implanted in a p-type silicon substrate 21 at 150 KeV and about 1E13 cm.sup.-2, and phosphorous is ion-implanted only in an n-type well formation region at 150 KeV and about 2E13 cm.sup.-2 by a lithographic process. The resultant structure is annealed to diffuse phosphorous and boron, thereby forming an n-type well region 23 and a p-type well region 22. A field oxide region 24 is formed on the p-type silicon substrate 21, and the resultant structure is isolated to form element regions. Thereafter, a gate oxide region 25 and a gate electrode 26 are formed in each element region.
Next, a resist film 30A is formed in the n-type well region 23 by a lithographic process, and phosphorous is ion-implanted at 40 KeV and about 1.5E13 cm.sup.-2. Similarly, as shown in FIG. 1B, a resist film 30B is formed in the p-type well region 22 by a lithographic process, and boron is ion-implanted at 15 KeV and about 1.5E13 cm.sup.-2. Thereafter, the resultant structure is annealed to form an n-type LDD diffusion layer 31 and a p-type LDD diffusion layer 32.
As shown in FIG. 1C, an oxide film is grown on the entire surface to have a thickness of about 200 nm, and the resultant structure is etched back to form an LDD side wall oxide spacer 33. A resist film 30C is formed in the n-type well region 23 by a lithographic process, and arsenic ions are selectively implanted in the p-type well region 22 at 50 KeV and about 3E15 cm.sup.-2.
Similarly, as shown in FIG. 1D, a resist film 30D is formed in the p-type well region 22 by a lithographic process, and boron fluoride ions are selectively implanted in the n-type well region 23 at 70 KeV and about 3E15 cm.sup.-2. After the ion implantation, the resultant structure is annealed at about 900.degree. C. to form an n.sup.+ -type diffusion layer 34 and a p.sup.+ -type diffusion layer 35 as source and drain regions.
As shown in FIG. 1E, an insulating interlayer 29 is deposited on the entire surface by a CVD method. The resultant structure is annealed to reflow the insulating interlayer 29, thereby planarizing the surface. Subsequently, a resist film 30E is formed by a lithographic process. As shown in FIG. 1F, contact holes are formed in the upper portion of the insulating interlayer 29 on the n.sup.+ -type diffusion layer 34 and the p.sup.+ -type diffusion layer 35 using the resist film 30E. After the formation of the contact holes, a resist film 30F is formed on the p.sup.+ -type diffusion layer 35 by a lithographic process, and phosphorous ions are implanted only in the n.sup.+ -type diffusion layer 34 portion through the contact hole at 70 KeV and about 5E15 cm.sup.-2.
In the same manner, as shown in FIG. 1G, a resist film 30G is formed on the n.sup.+ -type diffusion layer 34 portion by a lithographic process, and boron ions are implanted only in the p.sup.+ -type diffusion layer 35 through the contact hole at 30 KeV and about 5E15 cm.sup.-2. After the implantation, the resultant structure is annealed at about 850.degree. C. to form an n.sup.+ -type contact diffusion layer 37 and a p.sup.+ -type contact diffusion layer 38.
Finally, as shown in FIG. 1H, a wiring silicide is deposited by sputtering, and the resultant structure is etched by a lithographic process to form an electrode wiring 36, thereby completing a MOS transistor.
In the above manner, according to the conventional manufacturing method, when the n-type diffusion layer 34 and the p-type diffusion layer 35 as the source and drain regions, and the electrode wiring 36 which is to be connected to these layers are micropatterned, an n-type impurity and a p-type impurity are ion-implanted through the formed contact holes in order to avoid a leakage current caused by a positional shift between these layers and the contact holes, thereby forming the contact diffusion layers 37 and 38. For this reason, after the formation of the contact holes, a lithographic process and an ion implantation process are required again, thus complicating the manufacturing process.
Since margins for performing positioning between the diffusion layers 34 and 35 as the source and drain regions and the contact holes are set, the margins become obstacles to micropatterning of the source and drain regions. In addition, the margins do not allow an increase in contact areas, and become obstacles to reduction in contact resistance.
Further, annealing is required in formation of the contact diffusion layer, and annealing for reflowing the insulating interlayer is also required. Therefore, the formed diffusion layers as the source and drain regions are affected by the annealing, undesirably enhancing the influence of the short channel effect.